Increases in integrated circuit technology have resulted in a dramatic increase in the clock speeds of digital circuits have increased dramatically. Comparable advances in speed have not been achieved in Dynamic Random Access Memory (DRAM) arrays, with the result that data cannot be stored to or retrieved from DRAM arrays as fast as the data can be transferred into or out of a Synchronous DRAM (SDRAM) component at its data bus (DQ). To achieve high read data transfer speeds, many SDRAM components prefetch more data from a DRAM array than can be transferred on DQ in one cycle, and deliver the data successively, in a burst read operation. Similarly, the SDRAM component queues data from a plurality of data transfers in a burst write operation (also referred to herein as prefetching), and stores the data to the DRAM array in one cycle. By prefetching from and/or to the DRAM array, and pipelining burst read and/or write operations for contiguous data, the SDRAM component can achieve a higher data transfer throughput at the DQ pins than the DRAM array could support with single datum fetches and/or stores.
SDRAM components that support burst read and write operations typically prefetch data in a nominal prefetch data size that is determined by their internal architecture. The nominal prefetch data size determines the minimum burst length. For example, an SDRAM component with a 4-bit prefetch size—that is, it prefetches four bits of data for each bit in its data bus—would have a minimum burst length of four. However, in some applications, a shorter burst length is desired.
To accommodate a burst length less than the nominal prefetch data size, some DRAM components allow a burst data transfer operation to one DRAM bank to be interrupted by a data transfer directed to another DRAM bank. In this case (assuming data read operations), the SDRAM component prefetches the nominal prefetch data size (e.g., 4-bits per DQ bit) from the first bank in response to the first burst read request, buffers the data, and directs it serially to the DQ bus. In response to a burst read request in, e.g., the next cycle directed to the second bank, the SDRAM component prefetches the nominal prefetch data size from the second bank, and directs the data serially to the DQ bus with, in effect, a higher priority than the data from the first bank. From the arrival, at the DQ pins, of the data from the first bank until the arrival of the data from the second bank, the SDRAM component successively provides data from the first bank. When data from the second bank arrives at the DQ pins, the SDRAM component discards the remaining data from the first bank, and begins to successively provide data from the second bank. The second burst may run to completion, or may itself be interrupted by a request directed to another bank.
Although the interrupted burst operation achieves a burst data transfer of less than the nominal prefetch data size, it does so at the cost of expending the power to retrieve data in the first prefetch operation that is later discarded. Additionally, the interrupted burst operation results in successive, or “back-to-back,” DRAM array prefetch operations—each directed to a separate bank—which may exhibit some overlap. This increases the instantaneous power consumption of the SDRAM component. To compensate for the higher power demands, the power net in the integrated circuit is widened, adding to the die size overhead. The logic necessary to support the interrupted burst operation also consumes both integrated circuit real estate and power.